Help : Transformer Compilation error

[admin]

Hi,

Need help..

I just add a transformer and compile the code, hit the following error.
"Error when checking composite operator" The details are ...

>>Output from transformer compilation follows:
>>
>>##I TFCN 000001 15:20:24(000)
>>DataStage XE Parallel Extender V7.0.0
>>Copyright (C) 2003, 1997 - 2002 Ascential Software, Inc.
>>All Rights Reserved
>>
>>##I TOSH 000002 15:20:24(001) orchgeneral: loaded
>>##I TOSH 000002 15:20:24(002) orchsort: loaded
>>##I TOSH 000002 15:20:25(000) orchstats: loaded
>>##I TFSC 000001 15:20:25(003) APT configuration file:
>>/ascential/st1/default.apt
>>##E TBLD 000000 15:20:28(000) Error when checking
>>composite operator: Subprocess command failed with exit status 32512
>>##E TFSR 000019 15:20:28(001) Could not check all
>>operators because of previous error(s)
>>##W TFCP 000000 15:20:28(002) Error when checking
composite
>>operator: The number of reject datasets "0"is less than the number of

>>input datasets "1".
>>##W TBLD 000000 15:20:28(003) Error when checking
>>composite operator: Output from subprocess: sh: /opt/aCC/bin/aCC: not

>>found.
>>
>>##I TFCP 000008 15:20:28(004) Error when checking
composite
>>operator: /opt/aCC/bin/aCC +Z -O
>>-I/ascential/dsadm/Ascential/DataStage/PXEngine/include -O -c -ext -z
+Z
>>/ascential/dsadm/Ascential/DataStage/Projects/st1/RT_BP1.O/V0S2_lab1a_Transformer_2.C

>>-o
>>/ascential/dsadm/Ascential/DataStage/Projects/st1/RT_BP1.O/V0S2_lab1a_Transformer_2.tmp.o

>>(lab1a.Transformer_2)
>>
>>*** Internal Generated Transformer Code follows:
>>0001: //
>>0002: // Generated file to implement the V0S2_lab1a_Transformer_2
>>transform operator.
>>0003: //
>>0004:
>>0005: // define our input/output link names
>>0006: inputname 0 DSLink3;
>>0007: outputname 0 DSLink4;
>>0008:
>>0009: initialize {
>>0010: // define our row rejected variable
>>0011: int8 RowRejected0;
>>0012:
>>0013: // define our null set variable
>>0014: int8 NullSetVar0;
>>0015:
>>0016: }
>>0017:
>>0018: mainloop {
>>0019: // initialise our row rejected variable
>>0020: RowRejected0 = 1;
>>0021:
>>0022: // evaluate columns (no constraints) for link: DSLink4
>>0023: writerecord 0;
>>0024: RowRejected0 = 0;
>>0025: }
>>0026:
>>0027: finish {
>>0028: }
>>0029:
>>*** End of Internal Generated Transformer Code

--
Thanks & Regards
Samir V Chaudhari
Tel:+6 03 83158359